This invention relates to testing memory circuits, and more particularly, to testing integrated circuit memory blocks using built-in-self-test circuitry.
Memory blocks are often fabricated as part of modern integrated circuits. For example, application-specific integrated circuits and programmable integrated circuits such as programmable logic device integrated circuits may contain memory blocks.
Memory blocks may be provided in the form of arrays of random-access memory (RAM) cells. The memory blocks are used to handle the storage needs of the circuitry on a given integrated circuit. During normal operation of the integrated circuit, read and write operations are performed on the memory blocks.
Memory blocks on a programmable logic device are sometimes referred to as embedded array blocks (EABs) and may range in size from a few kilobits to about a megabit or more.
To ensure satisfactory operation of an integrated circuit that contains memory blocks, the memory blocks are generally tested during debug and design operations. Testing may also be performed during manufacturing.
It can be cumbersome or impossible to perform high-speed memory tests using only external test equipment. It is therefore often desirable to include internal test support circuitry on an integrated circuit to facilitate memory block tests. Because the internal test circuitry is incorporated into the integrated circuit that is to be tested, this type of test circuitry is sometimes referred to as built-in-self-test (BIST) circuitry.
A memory block built-in-self-test circuit supplies a memory block with test data while systematically stepping through the addresses for the memory block. If an unexpected result is detected in response to certain test data, the built-in-self-test circuitry can conclude that the memory block contains an error. Appropriate debugging or manufacturing repair operations may then be performed.
Conventional BIST architectures are satisfactory in certain situations, but can be inefficient when scaled to handle multiple memory blocks. For example, many conventional BIST circuits centralize address generation functions. Although this type of arrangement conserves address generation circuit resources, it places a burden on the address signal routing resources that are used on the integrated circuit. As a result, the area and complexity savings that might be obtained by centralizing address generation functions are offset by the numerous address distribution lines that are needed to distribute the centrally generated address.
It would therefore be desirable to be able to provide enhanced memory block built-in-self-test circuitry for testing memory blocks on an integrated circuit.